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PRELIMINARY
CY3140
ABELTM/SynarioTM Design Kit for FLASH370iTM
Features
* Device independent design entry formats: -- ABEL-HDL for ABEL-4, ABEL-5, and ABEL-6 -- Schematic entry, VHDL, and ABEL-HDL for SynarioTM * Full integration supporting all ABELTM and SynarioTM design features * Supports the full family of FLASH370iTM devices * Graphical device simulator included (CYPSIM) * Automatic installation into existing ABEL and Synario environment * Available on PC and Sun workstation design platforms
System Requirements
PC Platform 486-based IBM PC Microsoft Windows 3.1, 95, NT 16 Mbytes of RAM 8 Mbytes of disk space 1.44-Mbyte 3.5-inch floppy disk drive Sun Platform SPARC CPU Sun OS 4.1 or later 16 Mbytes of RAM 8 Mbytes of disk space
Introduction
The seamless integration of Data I/O's ABEL or Synario software design environment and the Cypress FLASH370i ABEL fitter offers a powerful solution for fitting ABEL and Synario designs into the Cypress CPLD device family.
Ordering Information
CY3140 ABEL/Synario Design Kit for FLASH370i includes: ABEL Fitter Software on two 3.5-inch floppy disks for PCs ABEL Fitter Software on 3 3.5-inch floppy disks for Sun ABEL Fitter User's Guide Registration Card Text (VHDL,ABEL-HDL)
Functional Description
The design process in the ABEL environment begins with entering ABEL-HDL (and optional test vectors) using any text editor. The process in Synario is guided by the Project Navigator, and begins with design entry in either schematic, VHDL, or ABEL-HDL. The design can then be functionally simulated at the source-level. It then goes through logic optimization and minimization. The output file then goes into the FLASH370 fitter. Test vectors specified in the ABEL-HDL files are also automatically processed for use in post-fitting device simulation. The FLASH370i fitter generates a JEDEC file for device programming and post-fitting simulation in CYPSIM. The test vectors will also be read in for functional verification. The post-fitting simulator, CYPSIM, operates under the Windows environment. It takes JEDEC files as input and can read in and write out stimulus files (e.g., test vectors from ABEL-HDL) for functional verification of the design. Users can edit input waveforms graphically and specify simulation length and resolution interactively. Signals can also be grouped, manipulated, and viewed in various formats.
Design Flow Manager (Project Navigator)
Sch
Functional Simulation Synthesis FLASH370i Fitter Program File (JEDEC) Device Sim (CYPSIM)
Available in ABEL and Synario Cypress FLASH370i ABEL Fitter Kit
Available in Synario only
Figure 1. ABEL/Synario Design Flow Document #: 38-00431-B FLASH370i is a trademark of Cypress Semiconductor Corporation. ABEL and Synario are trademarks of Data I/O Corporation.
Cypress Semiconductor Corporation
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3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 July 1995 - Revised April 1, 1997

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